ILAng

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New bug fix for function port declaration.

Bo-Yuan-Huang

**Describe your feature request.** Generate SMT formulas that use LIA or LRA for better support for CHC and other synthesis tasks. **Describe the solution you'd like** An option (additional to...

Bo-Yuan-Huang

Code significantly lacks comments, so we definitely shouldn't merge into master yet.

Anonymous-Stranger

Update Refinement Handling in Verilog Verification Target Generation

10

~~Work in progress, do not merge at this point!~~ This pull request is to see if the test coverage is sufficient.

zhanghongce

add time recording feature for ilator debugging

2

When `-DILATOR_VERBOSE=ON` is set during cmaking the generated sysmtec models, the execution time of each instructions will be recorded and dumped.

LeeOHzzZ

For preciese memory modeling in ILAtor, this commit use unordered_map instead of map to reduce the access time complexity from O(logN) to O(1) on average. Test with HLSCNN-ILA, and an...

LeeOHzzZ

**Describe the bug** Travis is not working so we temporarily stop it (because of some credit issue). We should figure this out and re-start it.

ILAng-service

LeeOHzzZ

**Describe your feature request.** - Separate refinement relation parsing & error checking from property generation. - Add expression parsing functionality so that in the future we can easily extend it...

zhanghongce

**Describe your feature request.** Support automatic serialization/deserialization of ILA models with hierarchy. **Describe the solution you'd like** Ser/Des hierarchy information (parent/child edges) for dynamic linking. **Additional context** State variable and...

Bo-Yuan-Huang