Pete Delaney
Pete Delaney
Looks very interesting to me. I really enjoyed working on JTAG support on the Tensilica ML605 fpga dev board.
I pulled the debug mode pull request and looked at it. It's rather large, my roommate works on Risc-v at TensTorent and is familiar with the Risc-v debug extension. I'll...
Example ML605 FPGA Support at Tensilica: https://wiki.linux-xtensa.org/index.php?title=SMP_HiFi_2_Development_Board
I tried merging Matthew-Otto's pull request and got a pre-hook failure. I'm not familiar with this. About to go for a swim, any tips? I'll take a look at this...
Dr. Stine: I'm very interested in working with you. At tensilica developed a SMP linux and I increased the JTAG debugging speed by 100x by making it like OpenOCD and...
Jordan any suggestions on dealing with this issue? I was thinking of seeing if ChatGPT had some suggestions and if tying to build would point out the things that needs...
James: I live in Silicon Valley so I'm not sure if we will have an chance to meet in the near future. If you do visit Silicon Valley I'm rather...
I fixed the lint errors and commited my 1st draft. I'm trying top and fpga builds. Pushed it to my github cvw repo: https://github.com/PietDelaney/cvw/tree/piet-30-June-jtag The cvw.lattest.jtag/src/debug/notes.txt has a good starting...
James: How's your work on the RISC-V DEBUG/JTAG work going? I've been busy preparing for HIP Surgery. Sigh!
Great James.