Philipp van Kempen

@andrewstevens-infineon My first attempt for a fully-compliant implementation using the arm semihosting extension spec: https://github.com/tum-ei-eda/etiss/commit/d054fb6537f53eaebe7c654bf4028a1e59d365bc It was easier than expected thanks to ChatGPT, yey... More testing is required before this...

> Looks plausible and likely to work... but why not just have the capabilities written to the tmpfile in a static byte array from the get-go? The tmpfile approach is...

In case you mean just hardcoding the whole file contents as a constant: That would indeed make more sense unless we want to add etiss config options to control which...

> Maybe just related: I’ve been thinking about user-level emulation and wondering how to properly set up a working argc/argv stack. My idea was to allocate a custom memory region...

@andrewstevens-infineon Thanks for sharing that file, this was exactly what i was looking for. C-level parsing should at least be better that porting ARM Assembly to RISC-V. The approach via...

@wysiwyng If this flow seems to work fine, we should extend it to automatically open up a PR with the new/patched Architecture. (Not only for S4EMAC but also RV{32,64}IMAFDC)

> [fix-semihosting-sys-read](https://github.com/tum-ei-eda/etiss/tree/fix-semihosting-sys-read) PR to upstream this is in the works. I just want to understand why the SYS_READ does not work without this fix and if the fix break file...

[fix-semihosting-sys-read](https://github.com/tum-ei-eda/etiss/tree/fix-semihosting-sys-read) can be dropped after #193 is merged.

For reference, the current work-in-progress ETISS RVV support developed @ TUW: - ETISS Fork: https://github.com/danielschloms/etiss/commits/daniel-dev/ - CoreDSL Code: https://github.com/danielschloms/RISCV_ISA_CoreDSL/blob/daniel-dev/RVV.core_desc - Softvector Fork: https://github.com/danielschloms/softvector/tree/daniel-dev/src/target/riscv

I do not see any issues with regard to the CoreDSL integration. MINRES softvector lib uses a similar style based on extern functions. Our approach uses one function per instruction,...