Philipp Kaesgen

Thank you for quick response! The L2s are private and inclusive. What I know so far is that two cores are writing to the same cache line. The DC sends...

You can take the same setup as in #1934 and use [out.txt](https://github.com/sstsimulator/sst-elements/files/9567745/out.txt) as described there. Add 10 to all mshr_latency_cycles to trigger this unhandled state.