Pedro Antunes

Is it possible to generate generic Liteeth Verilog?

1

Hi, Is there any way to generate the Liteeth Core Verilog independent of specific vendors? When generating the Verilog with the examples (`liteeth_gen wishbone_mii.yml`) the generated Verilog uses Xilinx modules...

Hello, ## Issue Description: I attempted to implement the [command referenced in the example Makefiles](https://github.com/wuxx/icesugar-pro/blob/ecc600a3d3e5fde940b0a69ffe2340d20c64a946/src/blink/Makefile#L20) for programming the IceSugar-Pro development board. Unfortunately, the provided command does not work as expected....