Orkun Ozkan

Hello, I hope you are all doing well. I am a regular user of LiteX, and I must say I love the direction it is heading in! I wanted to...

Hi @enjoy-digital Thank you for the update on TileLink bus feature in my previous inquiry. I appreciate your response. I have a follow-up question specifically regarding TileLink infastructure support on...

Hi @gsomlo, Thank you for the clarification. I have a follow up question on the topic of the cache coherency in a LiteX SoC with a Rocket cpu. I am...

Hi @gsomlo, Thank you very much for taking the time to respond to my questions. I truly appreciate your help, and I hope you're having a happy trip. I have...

> hope it helps This did, thank you very much. Ignoring my misconception on L2 cache existing on the Rocket cored SoC, and my lack of understanding of the coherency...

Hi @gsomlo, Thank you very much. This chat has helped ramp my understanding up quite well. I had one last question regarding how the SoC and the CPU interfaces. I...

https://github.com/enjoy-digital/litex/wiki/Reuse-a-(System)Verilog,-VHDL,-(n)Migen,-Spinal-HDL,-Chisel-core

Hi @gsomlo, I had a query regarding the lack of an L2 cache in the Rocket core module. Rocket offers L2 support through the `SiFive InclusiveCache` to produce a shared...

@gsomlo Could you not simply just add the inclusive cache generator within the `Config.scala` file within the update script for `pythondata-cpu-rocket`? Would it not be a drop-in replacement for the...

Hi @gsomlo, Through adding L2 cache to Rocket-core and building SoC `~/litex_environment/litex-boards/litex_boards/targets/digilent_nexys_video.py --build --cpu-type rocket --cpu-variant full --cpu-num-cores 1 --cpu-mem-width 2 --sys-clk-freq 50e6 --with-ethernet --with-sdcard --with-sata --sata-gen 1 --doc --csr-json...