XiangShan

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l2tlb: add dup register & add blockhelper & llptw mem resp select timing optimization

1

Lemover

Timing: merge MemBlock timing fixes

3

🐛？

cz4e

LoadQueueRAR: RegNext --> RegEnable

1

jin120811

Imporve gate coverage for DCache MissQueue and MainPipe. For control signals: `RegNext` -> `GatedValidRegNext` For datapath: `RegNext` -> `RegEnable`

bosscharlie

jin120811

Gate coverage lsq mdp

4

Gate coverage lsq mdp

jin120811

PPA memblock

6

jin120811

Bump difftest

1

This change will fix missing generated DifftestMacros.v when generating RTL.

klin02

prefetch: fix bug of sms evict

1

The performance comparison is as follows. | Commit | master-3c5d56 | fixSmsEvict | | | -------------------- | ------------- | ----------- | ------- | | 400.perlbench | 12.598 | 12.618 |...

Maxpicca-Li

rm refillPipe

2

YukunXue