OBarronCS
OBarronCS
This pull request brings an overhaul of the disassembly enhancement code, providing annotations alongside the disassembly in the `disasm` view to give context to the results of the instructions in...
This PR adds annotations to the `conditional select` category of AArch64 instructions. These instructions conditional execute an action, largely setting the destination register to some mutation of a source register...
This PR enhances the behavior of the disassembly of MIPS in regards to delay slots. The MIPS architecture has delay slots, which mean that the instruction directly after a branch...
This PR proposes setting the `show-retaddr-reg` config setting to `True` by default. Most non-x86 architectures that Pwndbg supports use a "branch-and-link" mechanism for calling functions, meaning instead of pushing the...
Currently, for each architecture Pwndbg supports, there is a single assumed calling convention for that architecture. These are defined in https://github.com/pwndbg/pwndbg/blob/dev/pwndbg/lib/abi.py. The codebase currently appears to assume the ABI that...
In disassembling the MIPS `JAL` instruction, a group indicating it is a CALL (or any type of jump) instruction is missing.  ### Instruction bytes giving faulty results ``` 0x04,0x00,0x00,0x0c...
Using Unicorn to emulate an Arm binary, I noticed a behavior where the stack pointer in the emulator is being reset to 0 if the `CPSR` register is written after...
This PR adds an indication that a pointer is referencing a free chunk in any heap pointers displayed in any use of the `chain` function (used in telescope, in printing...
This PR adds dozens of tests relating to our new cross-arch annotations feature. In sum, Pwndbg now has first-class support for RISC-V, ARM, AArch64, and the MIPS architecture as their...
This PR implements a new class based mechanism to represent architecture in Pwndbg. There are various different modules around the codebase that relate to inspecting the process based on the...