Nic30

I run tests of all our tools based on hdlConvertor and all seems to be pasign because the check already had to be performed. I hope that everyone else does...

Hello, for ```vhdl CONSTANT SHIFT_AMOUNT_SIZE : NATURAL := LOG2(DOUBLEWORD_SIZE) ``` the `LOG2()` is represented as index intentionally. It is impossible to precisely resolve because we do not know that `LOG2`...

Hello, situation is not nice. If the CALL is a default and INDEX is only in cases you you mentioned, we need to always translate the expression or we need...

This will require some API changes. 1. Extract shared code from `HdlComponentInstance` (name, parameter map, ...) to `HdlTemplateInstance` and then create `HdlPackageInstance` 2. Extract shared code from `HdlModuleDec` (name, parameter...

https://github.com/Nic30/hdlConvertor/issues/51#issuecomment-553518058 > analysis and visualization tools for HWT to VHDL/Verilog ecosystem Yes. The deadline is Christmas. But I think this will could be actually very complicated and as it is...

Actually, after the update of HWT API for hdlConvertor it would be possible to simulate the HDL in https://github.com/Nic30/pycocotb/tree/master/pycocotb/basic_hdl_simulator and others. It is actually not so far.

Yes, it is not converted to python https://github.com/Nic30/hdlConvertor/blob/master/src/svConvertor/statementParser.cpp#L199

@hs-apotell On C++ level there are 2 things. * It is possible to use ANTLR parsers directly and you will get full language support, all code positions etc. (I would...

@Thomasb81 it is parsed correctly, but it is missing in the parsed result. https://github.com/Nic30/hdlConvertor/blob/master/src/svConvertor/statementParser.cpp#L199

@mewais is now working on elaboration (as a hobby project)