Nic30

I deleted my comment with json format description and added it to readme of new project (format is slightly different than I told before). https://github.com/Nic30/pyDigitalWaveTools/ https://github.com/Nic30/pyDigitalWaveTools/blob/master/pyDigitalWaveTools/vcd/parser.py should do the job.

I also have D3 based renderer for this json format. But it is only prototype.  https://github.com/Nic30/hwtIde/blob/master/hwtIde/static/wave/app.js

I am not using D3.js as golden hammer (I hope so). It is just coincidence that two data-visualization project are well suited for this library. Also I think that JS...

For what the password is for? docker has secrets https://docs.docker.com/engine/swarm/secrets/#intermediate-example-use-secrets-with-a-nginx-service and travis itself can ecrypt keys https://docs.travis-ci.com/user/encryption-keys/

Hello @dvvgit , > I can send you a proposed diff if you are interested That would be nice, you can attach it to comment using just drag and drop...

@dvvgit Nice. Now, do you have at least some simple example so we can add it to tests?

Hello Thoob, the fix should be simple, however I want to know more about this problem first. Is this only a matter of the codestyle or it has also some...

Hello @Hovennnnn, do you want to check that the output file contains only Verilog-2005 compatible code or do you want to translate System Verilog syntax to Verilog-2005? hdlConvertorAst is a...

Hello, I think you are building against the wrong version of antrl4 (cpp runtime). You can try mesonbuild branch. see https://github.com/Nic30/hdlConvertor/issues/187#issuecomment-2122813878

Let me just add few keywords for better SEO. Microsoft RR-MSK-A-2040, Microsoft A-2040, A2040, Overlake: Celestial Peak, Microsoft Stratix 10 FPGA, MICROSOFT A-2040 M1132139-001 [Cloud and FPGAs in Physics and...