Mina2411

Hello, you mean to add a slave peripheral and fit it in the riscv soc, I need to do all the modifications in types_bus0_pkg only which is the index given...

I see also that there is no axi_master interface or it is implemented in the sv version under a different name, because I wandering how the master peripherals are connected...

so you mean that there is no module for AXI_master interface explicitly, sorry,I am not able to understand what you mean .

As I want to add a new master peripheral, how can I communicate with the AXI bus? That's why I am asking about an interface module like the axi_slv.

Hello again, I mas > 1. Yes. You need to create new AXI slave slot by increasing CFG_BUS0_XSLV_TOTAL value and defining allocated memory range in the CFG_BUS_MAP. > > 2....

[axi4_new_slave.txt](https://github.com/sergeykhbr/riscv_vhdl/files/11623343/axi4_new_slave.txt) For the testbench, I am working on it, but as you can see I made the connection the same as the connection of the sram and any other slave...

[riscv_soc.txt](https://github.com/sergeykhbr/riscv_vhdl/files/11623663/riscv_soc.txt) This is riscv_soc module, you can find the new peripheral under the sram module port map.

Hello, Yes,that was the problem, it worked now. also, I need to make my new peripheral non-cachable, so what I did that I tried to configure some CSR registers in...

You mean that I need to configure registers for PMP in the software program ?

I saw the pma module, and I didn’t understand what I should do to specify uncached memory regions, or I need to add something to the module itself