Mike Thompson

> Any name you prefer? I was thinking uvme_cv32e40p_mem_slv_vseq_c It could be useful if the seqence had a name that provided a hint that it implements the virtual peripherals. Also,...

Hi @silabs-robin, can you add a comment here to provide the command-line necessary to reproduce the above issue? Thanks!

Ah, sorry, I was not clear. What I'm most interested in is the command-line for individual tests that fail. You can get `ci_check` to give you that with the `-p`...

You are correct @silabs-robin, this is latent bug in `ci_check`. The script sets the simulator correctly for individual test runs, but not for building corev-dv. I'll fix it.

This is not directly related, but the init code needs to be aware of the [remapping](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/tb/core/mm_ram.sv#L300) done in the mm_ram.

> Move all of the generated test code (e.g. .S file for corev-dv, .elf, .objdump, etc.) into the "results" area. Not sure I get that. The current home is consistent...

Organize test-programs hierarchically. For example: - tests/programs/custom/plup - tests/programs/custom/debug - tests/programs/corev-dv/interrupt

Great stuff @silabs-robin. General question: are these assertions intented to be used for both formal and simulation? If so, which set of assumptions are required to use formal?

Hi @RanjanThales, what it the status of this PR? Can it be merged?

Thanks @RanjanThales. @JeanRochCoulon, @ASintzoff, @RanjanThales: I have added a "DO NOT MERGE" label to this pull-request until the CI issue has been resolved. @JeanRochCoulon, you will probably be the Committer...