Mike Thompson

I am re-opening this Issue as @JeanRochCoulon has requested a review of the MMU DV Plan.

Thanks for your interest in the CV32E40P @hansaniesamarasinghe. The information you are looking for would be considered proprietary to the owners of the PDK and probably the synthesis tools as...

Hi @gullahmed1251, I hope you meant to say "I just replaced the `

Hi @davideschiavone and @pascalgouedo, what is the status of this issue. I _believe_ it was agreed to fix it, but there hasn't been a resolution and the "waived" label was...

Hi @Attaullah786, did @pascalgouedo answer your question? If so, please close this Issue. If you do not comment within one week, this Issue will be closed.

Hi @Attaullah786' > there is no information about CPI for the test cases What do you mean by "CPI"? > Kindly give me insight about the test cases that gave...

The CV32E40P implements the [mcycle](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/control_status_registers.html#machine-cycle-counter-mcycle) and [minstret](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/control_status_registers.html#machine-instructions-retired-counter-minstret) CSRs. Your test-program could query these.

Hi @gullahmed1251, thanks for your interest in CORE-V. As you probably know, the CV32E40P supports PULP bit-manip as extended ISA instructions. The on-going CV32E40P v2.0.0 project is currently working to...

> I have read the details that in ALU of CV32E40P there are only few instructions for bit-manip. You would find it a lot easier to read the [User Manual](https://docs.openhwgroup.org/projects/cv32e40p-user-manual/index.html)....

@gullahmed1251, @gullahmed1, please reach out to me via email at [email protected]. I think we need to meet in person to move this discussion forward.