Mike Thompson

@MarioOpenHWGroup, are you saying: - that Spike can be configured to support the unprivileged counters CSRs such as cycle[h], instret[h] when `zicntr` is enabled? - we should add a new...

Hi @AyoubJalali, I am assigning this issue to you since you have made several contributions to `uvme_cva6_cfg.sv`. Feel free to assign it to someone else if that is appropriate.

@cathales and @zchamski, what is the status of this Issue?

My apologies @CoralieAllioux, I have not checked my Issues in a couple of weeks and I have missed this one. About your "suggested solutions": > since riscv_instr_gen_tb_top becomes cva6-dependent, copy...

Hi @frikhaAziz, can you have a look at this one?

Hi @ASintzoff. @JeanRochCoulon let me know that @frikhaAziz has completed his internship, so I am assigning this one to you.

Also, @SylRemTHA, please update this issue with the exact command-lines you use to create this issue, starting with `got clone ...`. Attaching a logfile would also be helpful. Thanks!

Thanks for this issue @spidugu444. I have assigned it to @JeanRochCoulon, the verification lead for the CVA6. As far as I know, the CVA6 team is not planning to support...

I have opened [CVFPU issue 63](https://github.com/openhwgroup/cvfpu/issues/63) for this issue. Please track debug of this problem in that issue.

Hi @Gchauvon, what is the proper value of `NR_RGPR_PORTS` for the CV32A6 v5.0.0?