Mike Thompson

Hi @dd-vaibhavjain, this issue has been long forgotten, but I believe it can be closed as the XPULP tests are running successfully on CV32E40P v2. Can you confirm this? Can...

Hi @ZElkacimi. As this Issue has not received any comments in almost 2 years and we do not believe there is an issue with the uvma_rvfi, I am closing this...

Still on my ToDo list...

Hi @silabs-hfegran, how was this issue resolved? Was a modification of the CSR test-generator required? If so, can you point to the associated PR? Thanks.

> as I understand the rest of the system is independent of the ISS as long as the RVVI interface provides the necessary data and the only part that needs...

Ah, I see I was not clear. Step-and-Compare does not used RVVI and ImperasDV. Step-and-Compare (both 1.0 and 2.0) used bespoke Tracers from the RTL (each one was unique to...

Hi @maolei-l, we do not track specific revisions of CORE-V-VERIF, except as it relates to a specific "core-under-verification". As each core achieves its verification goals we tag the specific version...

Yes, all CORE-V cores developed by the OpenHW Group use some version of RVFI. The best source of documentation for that is in the CV32E40S User Manual ([link](https://docs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest/rvfi.html)). S&C 2.0...

Yes, that is reasonably accurate. The tracer used for S&C1.0 was "ad-hoc" and not well documented, so your best bet is to look at RVFI. The differences between RVFI and...

Whether you use RVFI or RVVI is or any other interface/API to connect to the Spike ISS is your decision. For the CV32E4* class cores the distinction between RVFI and...