MauSilvestrini
MauSilvestrini
@dmitrym1 Hi, thanks for your work on XDMA driver. I used your patch on my design that implement Fifo AXIS C2H transfer by using Xilinx DMA/Bridge Subsystem for PCIe ip....
Hi @Prandr many thanks for your help. As I said before, during my tests sometimes high latency spikes btw two consecutive read calls occours, also please consider that I am...
Again, I ve to thank you for all your suggestions @Prandr. However, I actually forgot to provide you further details : 1. I ve chosen to insert the usleep delay...