Lunaphied

This isn't a valid behavior in Verilog correct? So Yosys isn't doing anything wrong by assuming that this is a valid way to initialize memories when translating the RTLIL into...

This is caused by the default standard used by macOS clang being very old, likely for compatibility reasons. The same major clang version (at least according to the output) on...

This essentially requires designing a new API surface for effectively specifying these signals. The current functionality with GTKW files is not ideal but works better than nothing for specifying top-level...

Just so we lay our thoughts out on these issues also: 1. We think the current format of documenting them in the docstring is reasonable enough, but we might want...

I think this is a relatively straightforward documentation improvement? Just to confirm the desire is that the bit on the left of the pattern is MSB and the right is...

We've been using Amaranth specifically on it's own to refer to the language in general. It amounts to a shorthand for the language itself. We've ended up using Amaranth HDL...

It looks and sounds like you're trying to synthesize a sequential circuit using loopback. This isn't supported currently. > Additionally, we are currently unable to synthesize sequential circuits, aka any...

Thank you for making us aware of `fs_per_delta` I can see us getting a lot of use out of it

What do you mean "not possible to implement"? This should be possible to render inside the GIF decoding portion and translate into a JXL compatible representation that is at least...