Lucas Klemmer
Lucas Klemmer
No, not at the moment. Although you can add new signals to a trace [like here](https://github.com/ics-jku/wal/blob/main/examples/virtual-examples/virtual1.wal), and I have an experimental (still private) branch that allows Surfer to connect to...
Hi, I think this depends a bit on how your simulator outputs array elements. For example, Verilator creates a signal `arra[0]`, `array[1]`, etc., for each element of the array. Since...
I see. Can you share the trace file or the signal names generated for your array?
You miss a pair of parentheses in the `let`. But that is probably my fault, I didn't keep the documentation up to date (fixed that now too). ```scheme (load "example.vcd")...
Great. If anything else comes up, feel free to contact me.
There are two systems for evaluating signals at different places. Scopes and groups. They work similarly but require different operators to resolve a signal. If you use groups you need...
In WAL there are no structs, only signals from the waveform. How structs are mapped to signals is up to the simulator. If you can produce a minimal example, I...
Ok, I spend a little more time with SV arrays and structs. This is something which I have not worked with much in the past. I simulated the following code...
Can you try the latest commit and let me know if that works for you? I have not used much "advanced SystemVerilog" constructs, so I am very happy to hear...
Hi, Thanks for being patient, I had a few very busy weeks. I had indexing problems like this myself. You can solve cases like this with a similar idea to...