Tang_E203_Mini

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Slow clock on Tang Primer board

2

What is the reason for `slowclk` running at only 32.786 kHz (8.388 MHz divided by 256) on the Tang Primer board? Especially since `slowclk` is driving almost all the logic...

andrsmllr

It would be nice to know why programming the bitfile to the EG4S20 FPGA via USB-JTAG takes a couple of minutes. The bitfile is only one or two megabytes in...

andrsmllr

Errors with Tang Prime

4

I've got the following errors with TD 4.4.433: USR-8132 ERROR: No net match the pattern: clk_16M. USR-8129 ERROR: e203egmini_new.sdc import error. GUI-8301 ERROR: Failed to read sdc e203egmini_new.sdc. Any clue?

agnunez

Add tutorial blogs from LicheeTang developers

5

Hi everyone! I found an interesting tutorial blog here: [Hello World on the Lichee Tang RISC-V/FPGA board](https://justanotherelectronicsblog.com/?p=470) written by @riktw The blog helps me a lot. Thanks! :smile:

liuqun

Is possible to increase ram to 400kb? for https://github.com/mruby/mruby

texrg