EDA-info

the awesome work, project and lab of EDA (Electronic Design Automation). continue update... (Because of personal reasons, we will not continue update...)

• Main EDA lab and open-source project：

  • Bei Yu, The Chinese University of Hong Kong
  • Evangeline F.Y. Young, The Chinese University of Hong Kong
  • Yibo Lin, The Peking Unbiversity
  • The UT Design Automation Laboratory (UTDA)
  • iEDA
  • Xuan Zeng, The Fudan Unbiversity

• Overview:

  • Machine learning and algorithms: Let us team up for EDA

• Placement and Routing

  • Routing:
    • FastRoute : A Step to Integrate Global Routing into Placement
    • NTHU : A New Global Router for Modern Designs
    • SAGERoute : Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility
    • Dr.CU : Dr. CU is a VLSI detailed routing tool
    • Dr.GR : Dr. CU is a VLSI global routing tool
    • Align : analog detailed router
    • Electromigration- and Parasitic-Aware ILP-Based Analog Router : analog global router
    • Efficient ILP-Based Variant-Grid Analog Router : analog global router
    • Reinforcement Learning Guided Detailed Routing for Custom Circuits
    • Pathfinding Model and Lagrangian-Based Global Routing
    • PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning
    • GAMER: GPU-Accelerated Maze Routing
    • COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing
    • Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints
  • placement:
    • Xplace : An Extremely Fast and Extensible Global Placement Framework
    • RePlace : Advancing Solution Quality and Routability Validation in Global Placement
    • DreamPlace : Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement
    • ePlace : Electrostatics based Placement using Fast Fourier Transform and Nesterov’s Method
    • MacroPlacement : Assessment of Reinforcement Learning for Macro Placement
    • MaskPlace : Fast Chip Placement via Reinforced Visual Representation Learning
    • RLPlace: Deep RL Guided Heuristics for Detailed Placement Optimization
    • Parallel Global Placement on CPU via Parallel Reduction
  • analog layout generation
    • Laygo : A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies
    • BAG : A Process-Portable Framework for Generator-based AMS Circuit Design
    • MAGICAL : Machine Generated Analog IC Layout
    • ALIGN : Analog Layout, Intelligently Generated from Netlists
    • Symmetry Annotation Extraction : Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks
    • Interactive Analog Layout Editing With Instant Placement and Routing Legalization

• Analog Circuit Design Optimization

  • Multi-objective Bayesian Optimization for Analog/RF Circuit Synthesis
  • Automated Design of Analog Circuits Using Reinforcement Learning
    • code
  • DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks
  • MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors
  • DC-Model: A New Method for Assisting the Analog Circuit Optimization
  • An efficient batch-constrained bayesian optimization approach for analog circuit synthesis via multiobjective acquisition ensemble
  • Batch Bayesian optimization via multi-objective acquisition ensemble for automated analog circuit design
    • code
  • Geometric programming for circuit optimization
  • A tutorial on geometric programming
  • Late Breaking Results: Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization
  • Learning to Design Circuits
  • GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning
  • Closing the Design Loop: Bayesian Optimization AssistedHierarchical Analog Layout Synthesis
  • Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization
  • Joint optimization of sizing and layout for AMS designs: Challenges and opportunities
  • Analog circuit sizing based on Evolutionary Algorithms and deep learning
  • Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing
  • Automated Design of Complex Analog Circuits with Multiagent based Reinforcement Learning
  • Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards
    • code
  • LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces
  • RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL
  • Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits
  • Bayesian optimization approach for analog circuit synthesis using neural network
  • A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench
  • High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure
  • A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization
  • An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis
  • A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis
  • APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors using DNN Learning

• Layout Pattern Generation

  • DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-Encoder
  • Layout Pattern Generation and Legalization with Generative Learning Models
  • LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling
  • DiffPattern : Layout Pattern Generation via Discrete Diffusion
  • WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout

• Pattern Layout Hotspot Dectection

  • Efficient Hotspot Detection via Graph Neural Network
  • Efficient Layout Hotspot Detection via Neural Architecture Search
  • Hotspot Detection via Attention-Based Deep Layout Metric Learning
  • Faster Region-based Hotspot Detection
    • code
  • Efficient Layout Hotspot Detection via Binarized Residual Neural Network
  • Hotspot Detection using Squish-Net
  • Detecting multi-layer layout hotspots with adaptive squish patterns
  • Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning
    • code
  • Lithography Hotspot Detection: From Shallow To Deep Learning
  • Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning
  • Bilinear Lithography Hotspot Detection
  • ADAPT: An Adaptive Machine Learning Framework with Application to Lithography Hotspot Detection
  • Many-Layer Hotspot Detection by Layer-Attentioned Visual Question Answering
  • Efficient Layout Hotspot Detection via Binarized Residual Neural Network