Junhao

About DFI to Xilinx Phy Interface

2

Hello, I read in your paper "We issue DRAM commands to the Xilinx DDR3/4 PHY IP [370] over a low-level DFI interface." Then because the Xilinx DDR PHY interface does...

How to use Xiangshan tutorial for multi-core testing about spec 2006

2

### Before start - [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。 - [X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。 - [X]...

About the clock problem in Xiangshan

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### Before start - [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。 - [X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。 - [X]...

How did Xiangshan achieve 10Mhz uart_16550?

2

### Before start - [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。 - [X] I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。 - [X]...

The xdma combined with bram test succeeded, but the test failed when replaced with ddr4

3

I first connected the IP of xdma and bram through block design, and then connected automatically. Then I put it on the board and tested it with run-test.sh, and the...

This PR adds the prototype of LG19A4_BOARD to openpiton. The FPGA of this development board is Xilinx's xcvu19p. The website of the development board is as follows: (https://www.tangoic.com/home). When using...

Problems encountered when using CVXIF to extend custom instructions

1

### Is there an existing CVA6 bug for this? - [x] I have searched the existing bug issues ### Bug Description I used the example given in this tutorial to...