LMiaoH

> Hi, I'm currently doing some benchmarking on XiangShan. I'd like to inquire if the core has the capability of actively invalidating the L2 cache through instructions or control registers....

Thanks. Unfortunately, trying these suggestions doesn't seem to have any effect, and the same issue persists. What should be my next move or consideration in this situation?

Thanks. I successfully implemented your suggestions. However, I'm wondering how long these test programs might take to run on Spike. For the `memcpy` function, we've been running it for over...

I want to execute the .asm file. Additionally, I attempted to use `--spike-disabled` to disable the lockstep check performed on the testbench, but I still encountered some issues: ``` NO...

Thank you, I think I might not have done that. But I am not sure how to use Gen64 to generate naxriscv. May it be as expressed in `src/test/cpp/naxriscv/README.md`?

Thank you, your approach is correct, but there is still an issue: encountering a floating-point register or fcsr register triggers a 'trap_illegal_instruction' message." ``` core 0: 0x00000000800003d2 (0x00305073) csrwi fcsr,...

Hello, I'm trying to inspect the values of certain memory addresses in `soc->memory` within the main.cpp file. However, the values obtained through the `get` function always return as 0. Could...