KotorinMinami

fix disassembly problems

4

Fix Issue #21 by adding function to deal with the sign number

extend Memory backend to dealing with various needs

1

We know that qtrvsim uses a memorytree with a fixed depth of 6, which causes its memory model to only accept 32-bit memory access instructions, thus restricting 64-bit access. This...

Memory access issue when xlen=64

1

In the new simulator phase, we can set xlen to 64. However, even after configuring it to 64-bit, the simulator's memory access range remains 32-bit, while the registers are 64-bit....

Function main in main.sail Not Reflected in C_emulator

3

In main.sail, the main function contains annotations for the PC (Program Counter) and uses a try...catch module for the correct operation of the simulator. ``` function main() : unit ->...

replace fsplit and fmake with mapping fstruct

2

As described in the TODO in fext and dext, I attempted to implement a mapping using floating-point number structures. Does it meet the stated requirements?

Remove N extension (user mode interrupts)

4

Since the RISC-V N extension draft was removed in the priv spec 1.2 version, the CSR sedeleg is also not listed in the CSR table in the spec. Therefore, it...

The sideleg CSR might be deleted

1

Recently, I reviewed the latest specification and found that the "sideleg" register no longer exists in the CSR table. Upon further investigation, it appears to have been removed. However, in...