Kocha
@raveensrk Thank you for contacting us. I have checked and corrected the problem. - [indent/systemverilog.vim](https://gist.github.com/Kocha/286beb6222a0f04a2ae4a2c792bfb42e) Could you please try it once. If there seems to be no problem, I will...
@raveensrk Could you please try this? - [indent/systemverilog.vim](https://gist.github.com/Kocha/286beb6222a0f04a2ae4a2c792bfb42e) Regarding the `ifndef` indentation, I have added an option. Once this is set, there will be no indentation. - `b:systemverilog_indent_ifdef_off `
Hi @raveensrk I think I'll go default ifdef indent on. Because that is what the example code in the IEEE1800 22.6.
Hi @raveensrk, Sorry to keep you waiting. Next... Could you please try this? - [indent/systemverilog.vim](https://gist.github.com/Kocha/286beb6222a0f04a2ae4a2c792bfb42e)
Hi @raveensrk, Sorry for the many updates. Next... Could you please try this? - [indent/systemverilog.vim](https://gist.github.com/Kocha/286beb6222a0f04a2ae4a2c792bfb42e)
Hi @raveensrk Thank you for response. - top.sv : `let b:systemverilog_indent_modules=1` option. - env.sv - Not support uvm macro indent. - Bugfix a few. -> [indent/systemverilog.vim](https://gist.github.com/Kocha/286beb6222a0f04a2ae4a2c792bfb42e) But, task close parenthesis...
HI @raveensrk I tried to solve `task close parenthesis` , but I am not sure if this is the right way to do it. Could you please try this? -...
@raveensrk Sorry for the wait. Updated the `indent/systemverilog.vim` file. - [indent/systemverilog.vim](https://gist.github.com/Kocha/286beb6222a0f04a2ae4a2c792bfb42e) If there seems to be no problem, I will issue a PR.
Hi, @raveensrk I sent to PR and closed. If all is well, please close the Issue. Best regards.
@Naireen Thank you for Reply. I tried debugging but didn't know where the problem was. Do you know which layer of `fasterrcnn_resnet50_fpn` is the problem?