Kevin-Andes

Attached the detailed description and diagram that David sent out to the TG discussion mailing list: [Tracking updated registers.pdf](https://github.com/riscv/riscv-fast-interrupt/files/5909980/Tracking.updated.registers.pdf) [ill#1c.pdf](https://github.com/riscv/riscv-fast-interrupt/files/5909985/ill.1c.pdf)

In the discussion of our Task Group meeting on 20210119, some member pointed out that the worst case scenario won't get improved with this approach. This is because, even though...

he definition in the current spec is valid and counts the number of bits in the comparator tree slightly differently. It is actually simpler: how many interrupt levels you need...

On a second thought, it is probably more confusing to define something like CLICCOMPAREBITS to be 10 bits. This is because 8-bit clicintctl already caps the interrupt level to be...

This dynamic sharing between interrupt mode and level bits is an OPTIONAL hardware optimization that only needed by some implementations (while other implementations may prefer to fix them). In addition,...

These CSRs are temporarily allocated in the read-write address range because we may have more read-write fields in the future. We may change this before we ratify the spec.

Intentionally leaving this issue open just to remind us to review these CSR address mapping before ratification.

#85 mentioned the following statement, but it is probably not true: "at some point in booting an OS the current interrupt levels will need to be set to 0 (so...

From: Tariq Kurd, Oct 21 2020, #193 Hi David, Thanks for this analysis. I added PUSHINT/POPINT to my proposal specifically for the interrupt handler, so any requests to change to...

From: Allen Baum, Oct 21 2020, #194 I see that there is a bias against microsequenced implementations for microcontrollers, as if they substantially increase... something. I see quite the opposite....