Kasper Hesse

Results 7 comments of Kasper Hesse

Feature request: Always advance clock by one cycle at the end of failed tests

Obviously that's a solution for tests that work, but for tests that fail, I can't find a way to inject a clock cycle when `expect` fails and raises an exception.

Feature request: Always advance clock by one cycle at the end of failed tests

I definitely think the circuit should be "idle", such that assert/printf statements do not get toggled. Otherwise, it might muddy the printout in the console I don't know much about...

Bundle literal construction outside test() is not allowed in Chisel 5.0.0 (works in 3.5.4)

Ok, sorry about the confusion. Closing here.

Bundle literal construction outside test() is not allowed in Chisel 5.0.0 (works in 3.5.4)

I also opened an issue on Chiseltest: https://github.com/ucb-bar/chiseltest/issues/690 and got the following reply from Kevin. > It looks like this is a Chisel problem and also it is probably fixed...

Fix incomplete merge with multiple covergroups in a covergroupCoverage

Hi Matthew, I think your proposal is also sound. However, your proposed example mixes coverage from the `sdt_slave` and the `master` components under the same heading, which I think could...

Fix incomplete merge with multiple covergroups in a covergroupCoverage

Hi Matthew, The XML file was produced using pyVSC. I manually cleaned it up a bit by removing some of our additional coverpoints for clarity, but I don't believe I've...

Fix incomplete merge with multiple covergroups in a covergroupCoverage

Hi Matthew, Sorry about the delay in getting back to you. I've put together a somewhat-minimal MWE so we can get better comparisons. Below are outlined two experiments I did...