Julian Kemmerer

Also reminded of https://github.com/JulianKemmerer/PipelineC/issues/97 Where by specifying a number of loops and pragma pipeline = "~each loop iteration is pipelined" - you are almost specifying the number of pipeline stages...

Confirmed this does break the implemented hardware after synthesis - without the timing loop bitstream behaves as expected...

Gah, made this issue thinking it shouldnt block whats in #86 But in testing it seems the rework that makes #86 almost done does need some ~optimization (not funcitonal) changes...

Actually will probably not require this change right away with #86 and can instead do at leisure when using results of combined #86 and instance array wires branch to do...

A similar but not as visible extra latency exists on the write side of the fifo valid in to valid out - running fifo near empty probably doesn't perform exactly...

Solution is to redo not using the built in dual port fifo prim, but raw VHDL fifo from fifo.h that can have more signals like clock enables that make feedback/buffering...

Broken still :fist: ```c #include "uintN_t.h" #pragma MAIN main uint16_t foo(uint16_t x, uint8_t y) { return x + y; } uint16_t bar(uint16_t x, uint8_t y) { return x - y;...

Small example ```c #include "compiler.h" #include "uintN_t.h" // Vivado works: //#pragma PART "xc7a35ticsg324-1l" // Quartus does not: "clk_25p0 could not be matched with a net" #pragma PART "5CEBA4F23C8" // Make...

Only the dumb auto generated clock input register using itself as clock is seen as the source of the clock :roll_eyes: `Node: pixel_0CLK_de264c78_clock_input_reg[0] was determined to be a clock but...

Thanks @suarezvictor prompting this into an issue