Julian Kemmerer

^ in the coming months should be able to squeeze in time for some kind of `--xo` option to make vivado produce an .xo file with those axi mappings are...

Might need to be `--xo_axis` specific to saying 'make an AXIS mapped IO .xo file' I think can infer which signals belong to axis by name `valid` `ready` `data` for...

More math fun :smirk: `Division algorithm in the CRAY-1 supercomputer.` https://www.ed-thelen.org/comp-hist/CRAY-1-HardRefMan/CRAY-1-HRM.html#p3-18

Yeah to anyone watching this issue or otherwise The PipelineC Discord is also a great place to also discuss this in a more conversational way https://discord.gg/Aupm3DDrK2 Down for brainstorming :brain:...

Thanks Bartus: https://essay.utwente.nl/79103/1/Kruiper_BA_EEMCS.pdf

Likely part of #46 and #48 too Once dealing with device specific netlists, might as well also see if tools provide .sdf output which should detail timing of each LUT...

Similar issue is wanting to optimize for area starts with first parsing area out of the reports from the tool... Similar to #45

I think it needs some clarification still @Datavenia Is the goal to move directories with .h files into `include//.h` ? I am not in a rush to get to this...

Thank you for considering looking into this. I did indeed forget that GHDL alone can convert to Verilog! I will absolutely try this :fist_raised: However, I feel like I once...

Sounding very familiar with Vitis HLS style stuff: https://docs.xilinx.com/r/en-US/ug1399-vitis-hls/pragma-HLS-pipeline `#pragma HLS pipeline` ex. ```c for (int i = 0; i < size; i++) { #pragma HLS PIPELINE II=1 out =...