Jakub Franek

'is_third_party' does not disable errors in third party libraries

6

Hello I am using vhdl-ls linter via TerosHDL integration in VS Code. I have a `vhld_ls.toml` file like this in the root of my repository: ``` [libraries] vunit_lib.files = ['.venv/Lib/site-packages/vunit/**/*.vhd']...

False errors reported in PSL statements

3

Hello, I am using the vhdl-ls linter as integrated inside TerosHDL extension in VS Code. I have a VHDL file, which I attach here: [clock_enable_generator.txt](https://github.com/user-attachments/files/18989684/clock_enable_generator.txt) (I had to change the...

**Describe the bug** I have an entity whose diagram in Module documentation is relatively wide, but looks fine there:  When I export Markdown or SVG, the diagram is saved...

Linting with VSG sometimes lints unexpected files

5

**Describe the bug** Linting with VSG sometimes unexpectedly lints VHDL files which are not interacted with in any way for unknown reason, which typically reside in TerosHDL folder. This leads...

Unable to set up VUnit

6

**Describe the bug** I am having trouble setting up VUnit with TerosHDL. I have a run.py script, which contains this: ``` from vunit import VUnit vu = VUnit.from_argv(compile_builtins=False) vu.add_vhdl_builtins() lib...

**Describe the bug** The following line is a PSL-style assert which is valid VHDL since version 2008 and runs fine in GHDL. `pulse_clk_count : assert always {reg_counter = COUNTER_MAX -...

mingw-w64-x86_64-yosys package does not contain plugins/ghdl.so file

5

Hello, I installed `mingw-w64-x86_64-yosys` package from the `mingw-w64-x86_64-eda` package group via MSYS2 on my Windows 10 machine as recommended in the readme. When I try to show a schematic view...

**Environment** VHDL Style Guide (VSG) version: 3.30.0.post5+git.37d0bea7.dirty Windows 10 **Describe the bug** I have a file with port_011 violation at path `vivado/LED_blink/LED_blink.srcs/sources_1/new/top.vhd`. I want to supress this violation for all...