jwhur

Is there a way to change syncing (?) interval?

1

I want to do some job on the file in mounted google drive. But whenever I try to save the file, it alerts annoying message that the file is newly...

Can't add edge to a non existing node

1

When I try to run a simple example on PyCG, it always raises exception `pycg.machinery.imports.ImportManagerError`. My setting is as follow: python version: `3.6.9` pycg commit: `99c991` I setup test directory...

**Type of issue**: bug report **Impact**: rtl refactoring **Development Phase**: proposal Hi, I found a new transient execution attack on risc-v boom. The attack relies on the bug #558, which...

source field in ProbeAckData

5

**Type of issue**: bug report **Impact**: unknown When RocketTile with Boom core receives PROBE_REQUEST message through tilelink b ports, it responds with with PROBE_ACK (_DATA) messages. The source fields of...

TLMonitor Assertion failure while running baremetal on BOOM

4

**Type of issue**: bug report **Impact**: unknown **Other information** I'm using SmallBoomConfig of riscv-boom v3.0.0 (without any modification). While running a bare-metal binary (which I modified from the SpectreAttack repo),...

Different result of fsqrt.s Boom vs Spike (Rocket)

1

**Type of issue**: bug report **Impact**: rtl refactoring **Development Phase**: proposal **Other information** I think there is a bug in floating point unit of Boom. The result of fsqrt instruction...

Invalid rm in floating point instructions

4

**Type of issue**: question **Impact**: unknown **Development Phase**: request | proposal **Other information** Hi, when executing Boom core with floating point instruction which has invalid rm (like 5 or 6),...

Behavior mismatch between Spike and Boom

2

**Type of issue**: bug report **Impact**: unknown **Other information** When I run fle.d instruction in spike and boom, Spike does not set FS bits in mstatus if both operands are...

Fix spr_eear to save appropriate value for each exception

1

This will resolve #99

When I input multiply, mtspr, multiply instructions sequentially, like this, ```verilog b08e1111 l.muli r4, r14, 0x1111 c011f416 l.mtspr r17, r30, 0xf416 b2160001 l.muli r16, r22, 0x0001 ``` value in r30...