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Jacajack
A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
Following functionality needs more test coverage: - [x] #259 - [x] `for` loops - [x] `if` statements - [x] `conditional` expressions - [ ] `wire` generics - [ ] generic...
We should gather all the ideas for the compiler frontend and implement it, rahter sooner than later. - [ ] Test the exacutable via python scripts (maybe ressurect fuzzing) -...
### Feature description
### Feature description Registers should have an optional input called `reset_value` specifying register value after reset. If not present in the binding list, it should be assumed to be 0.
Let's clean up all warnings in our code and run `cargo clippy`. After that we should embrace zero-warning policy on `main` branch enforced by the CI. - [x] #290 -...
### Input ```sv module big_or { int WIDTH; int NUM_INPUTS; input clock clk; input comb(clk) ubus inputs[NUM_INPUTS]; output comb(clk) ubus out; } impl big_or { // Assert NUM_INPUTS is positive...
### Feature description