IC-Dream

Hi, @ethanhz, here is the disassembly:  I think that the "sw " of line 12 ~ 26 might introduce this error. Thanks Dream

Thanks a lot, Yea, i noticed that the linker is always starts from 0x8000_0000 in riscv-test(https://github.com/riscv/riscv-tests), and I try to modify the code start address to 0x8000_0000, there is some...

so, could you please show me how to allocate the address space in spike ? or any reference for spike ? thanks a lot.

Yea, i have tried modified these lines you pointed out like this, but i would get some build errors when build c code. instrram : ORIGIN = 0x80000000, LENGTH =...

Hi, @luismarques, I also enounter this issue, and the spike hangs and can't exit. so do you know the flow of spike exit, for the ELF form riscv/riscv_tests, it would...

@luismarques thanks a lot， i added the tohost and fromhost symbols in .ld files and jump to write "1" to tohost in the end of test case. the spike can...

@seldridge Hi, is there any ways to improve the score of dhrystone benchmarks ? I try to modify the CFLAG of riscv64-*-gcc to compile the dhrystone, but still can't reach...

Hi, I built the riscv-tests by default, using the makefile in the github, and there is one rvc.s to test RVC instructions set in ~/riscv-tests/isa/rv64uc, but I found that the...