HeathenUK

I wonder if there's any way to track DMA calls. Of course part of the point is that the 8088 is out of the loop... In any case, I don't...

I suppose without access to the ISA bus signals not tapped by the 8088 you'd need to trap writes to the I/O ports for DMA control registers and channels 1...

Related - I've just clocked that the various bits of runtime (mode==1) conditional code in the accelerated version are commented out. It looks like most of that is about ROM...

(Apologies for the confusion, switching out of the other account which is otherwise inactive) Thanks for getting back to me, hugely appreciated! I'm looking to adapt your design for my...

Thanks for running the thought experiment with me! I have a couple of follow-up thoughts if you don't mind: 1. I assume there's no issue with tying the same clock...

Thanks for all the advice so far, it's been really helpful! I've been radio silent on this for a few days as I've pondered how to balance the constraints here...

Hmm, thanks. Can I ask a couple of questions? - Which of the enables did you intend to be active low on the first MMU you described? I assume A23/22...

On your first response - I see! I thought there was some timing reason for using CLKFAST#, it didn't even occur to me that it was because you'd used up...

> Maybe I could propose another solution that uses only one MMU but a bit of additional decoding logic. This solution would give you 4 RD/WR pairs and also the...

I'm actually really excited by your original proposal (dual "MMU")! I think I can work around the one limit it creates. As an aside I've just been skimming the monitor/bios...