Verilog-FIR
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20 hours ago •
Grootzz
Grootzz
FIR implemention with Verilog
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Verilog-FIR issues
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hello, while trying to simulate the code on Xilinx Vivado, I'm getting no output at the o_fir_data_tb pin, and the input is latched to 16'h7FFF, please help me out here...
