Greg Chadwick

I've added some stuff and reworked commits here to give https://github.com/lowRISC/ibex/pull/1811 which supersedes this PR and should get the memory integrity test running and passing.

This is no longer relevant (cosim has long been integrated via a different PR), so closing

Add a sentence about adding coverage for this, shouldn't be complex given the rest of the PMP stuff is already there so didn't alter the estimate.

#1808 gives us the basis of this (random `CPUCTRLSTS` writes will enable/disable random instruction generation). Currently the dummy instructions are simply not fed through the RVFI interface so the cosim...

I'll take a look at this as I'm more familiar with the co-sim side of things than @marnovandermaas and it'd be good to get a rapid fix on this.

Sorted out passing through the PMP config in this PR: https://github.com/lowRISC/ibex/pull/1766 Though there's more to it. - We need to make PMP CSRs illegal in non PMP configs: https://github.com/lowRISC/ibex/pull/1767 -...

Further work here, riscv_mem_error_test was broken under the opentitan config. This was down to PMP. RISCV-DV sets up PMP regions by default and riscv_mem_error_test did some accesses that generated PMP...

This has now been fixed https://github.com/lowRISC/ibex/pull/1800 (though required the removal of the branch predictor config from CI)

Hi @jtate-pu, have you done any further work on this? As a first step a proposal for the modified bus protocol would be good. The extra bits to give an...

I'll look at updating the timeout. I can run a test regression on my workstation to quickly determine the impact of a larger timeout.