Greg Chadwick

@hcallahan-lowrisc to merge @marnovandermaas's Ibex changes

With https://github.com/lowRISC/ibex/pull/1876 this test is now behaving reasonably

@hcallahan-lowrisc have you come across any behaviour around single stepping and interrupts in your debug DV work?

The first thing to check is how did you build the simulation? You may have configured Ibex to have no performance counters, hence the results.

> That means we won't differentiate between seeing an integrity error on the memory interface while doing a store or a load (either way if rdata integrity bits are faulty,...

Oh and we do need a check that an integrity error triggers an alert. This can be done as an assert for the data side. Instruction side requires a little...

As discussed in the Ibex DV Sync I think we should avoid generating integrity errors in the `riscv_mem_error_test` and introduce a new `riscv_mem_error_intg_test` that does have integrity error. Just add...

> I think this PR increases our test time for mem_error_test (after changing it with the new sequence we probably are injecting way more memory errors) and tips it over...

> @GregAC can you have a look at [66d8d0f](https://github.com/lowRISC/ibex/commit/66d8d0fc0b087fa48f74cf8e0d343b582e2ad8e9) to see if this makes sense? It does make sense, though having reviewed our discussion I think we want to leave...

> > @GregAC can you have a look at [66d8d0f](https://github.com/lowRISC/ibex/commit/66d8d0fc0b087fa48f74cf8e0d343b582e2ad8e9) to see if this makes sense? > > It does make sense, though having reviewed our discussion I think we...