Greg Chadwick

We could do this via a directed test that expects specific values for the counters at the end.

estimate range: 2 - 4

estimate range: 4 - 8

Estimate range: 2 - 4 These should be mostly/entirely filled by the directed test work. Remaining work is to get that running in nightly regression and assess coverage impact.

New directed tests have significantly improved PMP coverage. Some small holes remain but these are mostly low priority. We still don't hit the U mode related error cases in `pmp_iside_nomatch_cross`...

From a recent regression run (outside of the standard nightly regression so the full directed test suite could be included) remaining PMP holes are all around attempting to execute code...

Directed test to stimulate U mode execution of locked regions in PR here: https://github.com/lowRISC/ibex/pull/2052 this closes the relevant coverage holes.

Addressing the remaining holes is a V3 issue

> Besides manual modification of the HDL, is there a way of including the Register File (FF) in the Instruction Decode stage ? In the current version I see that...

We tend to run simple system using Verilator so it's possible it's currently broken on Xcelium. `DV_FCOV_SIGNAL_GEN_IF` is a macro defined here: https://github.com/lowRISC/ibex/blob/master/vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh I note that `dv_fcov_macros.svh` should be included...