Guillaume Chauvon

After this line : https://github.com/openhwgroup/cva6/blob/e4b48a794b0229eeb9264a6b3f459c86545d1d85/corev_apu/fpga/scripts/run.tcl#L72 You can save the project to open it in GUI mode by adding this to the script : ``` #save_project_as ariane_gui #exit 1 ``` You...

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Done for 64b Linux. Not started for 32b Linux, it is part of step 1 verification schedule.

While integrating some founders memory RAM controller in CVA6, I ran into this error as well. I'm quite interested in a fix. I'm not familiar with the verilator code, so...

Source files management complexity is due to 2 reasons : - Historical reason, everything was in the Makefile at some point - Multiple testbenchs and simulators which works with common...

Hello, I don't think it is a bug. It is a choice I made when implementing CVXIF in order to not increase size of the register file when cvxif does...

Yes if you want to use 3 source registers, you have to change the RTL because it is not the default configuration of CVA6.

It's `NR_RGPR_PORTS=2`

We could add this parameters in the config_pkg. It can be part of CVA6 parametrization.

Reset is asserted before before 1st clock cycle leading to weird transition on the AXI agent side. I believe clock and reset is not well configured.