Forty-Bot

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Expected overheads / available capacity

The overhead can be calculated from the memory layout: ``` Memory layout ============= This is a memory layout example with the following configuration: * log2_ppc = 2, ie check point...

Expected overheads / available capacity

> This would reduce the overhead to 12.5% (7 metadata pages per block, plus one unused page). Actually, I forgot the ppb is 256 with 512-byte pages, so the overhead...

Expected overheads / available capacity

OK, so I did some write amplification experiments. I used the flash parameters from above, simulating a 100 MiB area. I tested sequential and random writes. Here's what I found:...

Fix post-synthesis simulation in yosys

For reference, I'm instantiating this like ```verilog lfsr #( .LFSR_WIDTH(32), .LFSR_POLY(32'h04c11db7), .LFSR_CONFIG("GALOIS"), .REVERSE(1), .DATA_WIDTH(8), .STYLE("REDUCTION") ) crc ( .data_in(data), .state_in(crc_state), .state_out(crc_state_out) ); ``` Your changes work, but now the module...

Fix post-synthesis simulation in yosys

> Well, to some extent taking longer is expected For reference, I go from ``` real 0m3.318s user 0m3.252s sys 0m0.061s ``` To ``` real 0m26.285s user 0m25.974s sys 0m0.257s...

Fix post-synthesis simulation in yosys

> TBH, I don't care all that much about build times I care very much about build times. I regularly run post-synthesis tests on modules to make sure I don't...