Finn Wilkinson
Finn Wilkinson
In the current implementation, the immidiate value for the SVE `dup zd, #imm{, shift}` instructions is limited to 8-bits. However from the Armv8 ISA specification it states that for vector...
Current helper function implementation is verbose (i.e. most instruction types have their own helper function). However, a better implementation would be a series of generic helper functions which can be...
This PR implements all available SME (version 1) instructions that are contained within LLVM 14.0.5. Specifically, this is [Version 2021-06 of the Armv9-A A64 ISA](https://developer.arm.com/documentation/ddi0602/2021-06/SME-Instructions?lang=en). No FP16 or BF16 instructions...
Currently, the dispatch issue unit will get one port allocation and if the attached Reservation station is full or has exhausted its dispatch rate for that cycle, the port will...
This PR updates SimEng to work with a newer release of Capstone who's AArch64 engine is based on LLVM18, hence allowing SME2 support. The reccommended version of LLVM has also...
### Work environment | Questions | Answers |------------------------------------------|-------------------- | OS/arch/bits | MacOS AArch64 | Architecture | armv8 | Source of Capstone | `git clone` | Version/git commit | df7228674963b8bc0fe6e00c29e13c731a665d41 Sorry...
Updated opcode enums for latency group 11 in both a64fx config files as they changed when capstone was updated.
This PR adds a wide range of different NEON, SVE2, SME2 instructions with regressions tests. These facilitate a subset of some internal SME-based GEMM and GEMV codes. There is some...
Update the `trace` branch to be inline with `dev` and add support for SST so traces are generated with SimEng and SimEng+SST simulations.
The A64FX port allocator triggers an assertion in debug mode after the new Dispatch Issue Unit updates. The A64FX port allocator assumes the ports provided will be all possible ports...