Filip Gherman

- This project builds only with this update: https://github.com/analogdevicesinc/hdl/pull/939! - Was not tested on hardware!

In case of using JESD configurations with more than 6 lanes, Master Clock Generation Block(mcgb) must be enabled for both bonding and non-bonding clock cases when using Stratix 10 H-Tile.

Reference design for AD9213 evaluation board

axi_dmac: Add suport for 64 bit address width

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Tested with the following testbench: https://github.com/analogdevicesinc/testbenches/tree/dev_DMA_64bit Currently testing in hardware with the following use case for ZynqMP with DAQ2: https://github.com/analogdevicesinc/hdl/tree/ZynqMP_DDR_HIGH

## PR Description In case of JESD configurations with the number of lanes higher than 16, the software could not access any DRP information of the GT channels and the...

ad_quadmxfe1_ebz: Fix critical warnings

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## PR Description Fix Critical Warnings for the Quad-MxFE Project on VCU118: -Connect adc/dac_sync_manual_req_in signals in the BD Signed-off-by: Filip Gherman ## PR Type - [X] Bug fix (change that...