EdwinEstep

Results 2 issues of EdwinEstep

State Machine Viewer draws nodes containing `*initial*` differently

**Describe the bug** The state machine viewer draws any node containing the substring `initial` as a circle, with no name attached: This can cause issues. For example, if you have...

bug

`test_ip_eth_tx_64.py` hangs

4 comment

After the latest commit to `ip_eth_tx_64.v` (`9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2`), the MyHDL testbench hangs indefinitely: ![image](https://github.com/alexforencich/verilog-ethernet/assets/61259473/41da47fd-ef50-4157-9fec-999682c86701) The only changes I made were to tell the testbench where to find the myhdl VPI bindings....