Divya2030

Merge multiple coverge reports

4

Hi, i have generated multiple coverage xml files using vsc.write_coverage_db("cov.xml") . How to merge multiple xml files. is there any method to merge multiple xml files?

Hi @mballance , I have written multiple covergroups and in pyucis-viewer its printing coverage percentage of each covergroup,is there any way to find the total percentage of all covergroups in...

Support sequence

2

I am attempting to use Verilator 5.015 for RTL simulation, and I've run into issues related to Verilator's support for SystemVerilog Assertions (SVA). **Issues Faced**: 1. Verilator does not support...

Surelog Not Flagging Missing Time Delays, and Undefined Property References

9

**Original Tests Link** [clock_divider_original.zip](https://github.com/chipsalliance/Surelog/files/12462317/clock_divider_original.zip) **1. Property missing delay operator (##8) passes without error on line 39 clock_divider.sv** [clock_divider_ex2.zip](https://github.com/chipsalliance/Surelog/files/12462403/clock_divider_ex2.zip) ```systemverilog property p_clk_out_toggle; @(posedge clk) !reset && clk_out |-> !clk_out; endproperty ```...

Document code coverage collection

12

how can we find code coverage?