David Tyler

Results 31 comments of David Tyler

I have a feeling that all the complexity of open bus shouldn't exist in my emulator since I'm emulating the D signal values at cycle level accuracy. At heart open...

https://github.com/nba-emu/NanoBoyAdvance/blob/68eb934fe2eabdbe41d554912483331f81decc60/src/nba/src/bus/bus.cpp#L275

![image](https://user-images.githubusercontent.com/1358414/161301874-420f0d63-396a-4f71-ab29-4c8bd5e14d6c.png) 1234/2020 passing as of today with timers working fairly well. IWRAM tests pass each time so the instructions themselves are about right. Likely to be issues with prefetch unit...

Fixes for DMA to share wait states with CPU have caused massively broken DMA tests ![image](https://user-images.githubusercontent.com/1358414/161302081-29b8269d-3c03-4892-b87d-1a0d177dd091.png) needs investigation

![image](https://user-images.githubusercontent.com/1358414/162830089-65f242f5-4f2b-4806-b1d7-373d943866c3.png) I've fiddled around with this a bunch tonight and got to 1341 (have had it higher but probably by accident). Specifically now the standard NOP tests all time correctly...

![image](https://user-images.githubusercontent.com/1358414/162997546-0657a7d6-b700-4075-a75b-36e365aaad8c.png) The key learning here that fixes prefetch is that prefetching is always sequential (obviously) and pays no attention to the state of the SEQ signal from the CPU if...

![image](https://user-images.githubusercontent.com/1358414/162998324-b32a5c14-078b-48d4-a5a1-9f81360ff03a.png) that's an example of DMA timings

![image](https://user-images.githubusercontent.com/1358414/163000446-e518dde0-86a4-4329-b4ee-5d79d44f8b19.png) Multiplication failures, implies that the timing is off entirely, nothing to do with prefetch but only for thumb. Which is odd since they use the same code!

Multiplication issues are resolved, they were caused by incorrect operand ordering for masks. BIOS calls from thumb are not resolved though, so presumably there's something in there about switching from...

Fix bios timings by clearing the prefetch unit when the pipeline is cleared