Dave McEwan

Width of enum members with explicit value is not detected.

1

Warnings are emitted only for the localparams `CATPK_IE_BIT` and `CATPK_IE_LOGIC` below. It's odd that the other permutations detect the correct width and don't warn. The warnings are only emitted when...

Add fuller explanations about each rule.

3

- Add a new member `explanation` to each rule. - Adjust the formatting of `RULES.md` (via `mdgen`) to be slightly easier to read. - Adjust `hint` and `reason` to be...

New Rule: `style_trailingwhitespace` to catch trailing whitespace.

1

Trailing whitespace causes issues with git.

Parameters in generate blocks are treated as localparams, so detect confused/alias keyword. IEEE1800-2017.

Detect non-sensical cases like this: ```systemverilog assert (foo) begin: pass_action_block $display("IO says it passed"); // Usually replace with $info, or perhaps $fatal, $warning, $error. end: pass_action_block else begin: fail_action_block $display("IO...

Allow indented assignment to with concatenation on LHS. This code structure is useful for tying off lots of wires: ```systemverilog assign { foo , bar , baz[i][j][k] } = '0...

Methods declared like `pure virtual function foo` or `pure virtual task foo` are only allowed inside a virtual class (declared like `virtual class foo`) or an interface class (declared like...

New Rule: Check that filename matches module/interface/package/program identifier.

2

Modules, interfaces, packages, and programs are often requried to be declared in their own file. A new set of rules should check, for example, that `module Foo; ... endmodule` lives...

Feature: Extend rules mechanism to further levels of abstraction (long term).

1

This describes a long-term project for extending the rules mechanism in svlint. As discussed briefly [here](https://github.com/dalance/svlint/pull/224#issuecomment-1422900590), it would be nice to have rules for different levels of SystemVerilog abstraction. It...