Digi

Problems related to asSint type conversion to verilog file (.sv)

1

in the version chiselVersion = "5.0.0" chiseltestVersion = "5.0.2" version riscvmini: the code in datapath ``` ` val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)( Seq( LD_LH -> lshift(15, 0).asSInt, LD_LB -> lshift(7,...