Christian

Synthesizing a generated SoC with Yosys?

4

Hi, I'm trying to generate an SoC with Chipyard and then pass the design to OpenLane for automated RTL-to-GDS. I'm running the simulation for the example RocketConfig and then attempting...

Using Yosys supported SystemVerilog?

3

Hi, I'm trying to run a design that includes SystemVerilog in the design, but only the Direct Programming Interface (DPI) which is supported by Yosys According to the docs "SystemVerilog...