Ceridli

Signal integrity issue for VLSI is somewhat different. Its effect depends on the arrival times of the signals to have a significant effect on timing. That depends on a lot...

Unfortunately, I stopped writing for quite some time. However, it is not rocket science. There are two issues here: When there is capacitive coupling between the nets, (i) from driven...

By the way, for the first effect, it is just a static calculation. You don't necessarily need an STA engine. You can run through actual simulation, with passive victim drivers...

Thanks for the response. I was not familiar with 'bender' methodology. I liked the idea though. It could be especially useful if you are doing transaction level verification. Different tools...

Thanks. I suppose one can fashion one mimicking the get_property command in tcl/Sta.tcl. On Fri, Jul 7, 2023 at 11:52 AM Vinayakamk ***@***.***> wrote: > in opensta version 2.0.17(as im...