bkilambi

8290249: Vectorize signum on AArch64

4

This patch auto-vectorizes Math.signum intrinsic for float and double types on aarch64 (Neon and SVE). On SVE supporting machines, if the MaxVectorSize 16, the SVE code for the intrinsic would...

8293488: Add EOR3 backend rule for aarch64 SHA3 extension

6

Arm ISA v8.2A and v9.0A include SHA3 feature extensions and one of those SHA3 instructions - "eor3" performs an exclusive OR of three vectors. This is helpful in applications that...

8320725: C2: Add "requires_strict_order" flag for floating-point add-reduction

31

Floating-point addition is non-associative, that is adding floating-point elements in arbitrary order may get different value. Specially, Vector API does not define the order of reduction intentionally, which allows platforms...

8330021: AArch64: Add backend support for FP16 add operation

3

This commit [1] adds initial support for FP16 operations and adds backend support for FP16 add operation for X86. This task adds backend support for scalar and vector FP16 add...

8336406: Add support for FP16 binary operations

5

This patch adds middle end support in C2 for a few FP16 binary operations, namely - subtract, multiply, divide, min and max. It also adds aarch64 backend support for these...

FP16 isNaN, isFinite, isInfinite intrinsics without Reinterpret nodes

2

This patch removes the ReinterpretS2HF nodes in the mid-end during the generation of isNaNHF,isFiniteHF and isInfiniteHF nodes. Performance results for this patch on an aarch64 machine - ``` Benchmark Gain...