Axionix77
Axionix77
The configuration is 64-bit (with 8 expWidth and 24 sigWidth). The testbench is a formal one. We are comparing the hardfloat model against our formal model. Our models ended up...
Yes, you are right. I meant to write 11-bit exponent and 53 bit significand.
The testbench is using formal assertions. The mismatch in the design and the formal model is getting exposed for the case when the exponent is all zeros (subnormals). On constraining...
Our testbench is testing the equivalence of the hardfloat with an SVA model. The hardfloat comparison operation uses recoded values not the IEEE754 , so we've put together a wrapper...
Thank you for your reply. I will add it to the other repository.